1. Field of the Invention
The present invention relates to an apparatus for manufacturing semiconductor integrated circuit devices, and more specifically to a semiconductor die bonding apparatus having a die pickup tool with multiple contact parts for preventing electrostatic discharge from damaging the semiconductor integrated circuit devices during the manufacturing process.
2. Description of the Prior Art
In manufacturing semiconductor integrated circuit (IC) devices, a semiconductor wafer which includes a number of semiconductor chips is produced. Then, the assembly of the semiconductor chips starts with a sawing step which separates the semiconductor wafer into individual semiconductor chips. After the sawing, a die bonding step bonds the semiconductor chips to a lead frame. A die bonding apparatus picks up the semiconductor chips by using a tool which is commonly called a pickup collet, a transfer collet or a bond collet.
FIG. 1 shows a conventional pickup collet 10. As shown in FIG. 1, pickup collet 10 includes a collet body 12 and a vacuum line 14. A hole 16 in collet body 12 extends through vacuum line 14 and is used to create a vacuum. As used herein, the term "vacuum" includes any pressure less than the ambient pressure that will cause a chip to be held against the pickup collet. This vacuum holds a semiconductor chip such as semiconductor chip 20 of FIG. 2 in a contact part 18 of collet 10, and blowing air or nitrogen gas through hole 16 releases semiconductor chip 20 from collet 10.
During the manufacture of semiconductor devices, the equipment or operator often produces an electrostatic discharge (ESD), and the electrostatic discharge can damage semiconductor chip 20 by causing a breakdown of the insulation or breakdown of integrated circuits. In particular, pickup collet 10 is one of the most noticeable sources of electrostatic discharge.
A top surface 28 of semiconductor chip 20 is, as depicted in FIG. 2, covered with a passivation layer 22 for protecting circuits. However, chip pads 24 and fuses 26, which are made of a metal such as aluminum, should be exposed for wire-bonding and repairing semiconductor chip 20 according to the results of electrical die sorting, respectively. Therefore, when collet 10 picks up semiconductor chip 20, chip pads 24 and fuses 26 are in close proximity, without any interposer, to contact part 18 of collet 10, as illustrated in FIG. 2. The dashed lines in FIG. 2 show the area where contact part 18 contacts top surface 28 of semiconductor chip 20. Accordingly, chip pads 24 and fuses 26 became susceptible to ESD damage.
Two typical examples of electrostatic discharge caused by using conventional pickup collet 10 are shown in FIGS. 3 and 4, which are cross-sectional views taken along the line III--III of FIG. 2. FIG. 3 depicts the alignment of semiconductor chip 20 on an aligning stage 30 before bonding chip 20 to a lead frame, and FIG. 4 depicts the picking up of semiconductor chip 20 from a sawed wafer 50 attached to a sawing tape 40.
Referring to FIG. 3, when collet 10 places semiconductor chip 20 on aligning stage 30, air or nitrogen gas is blown through vacuum line 14 to release semiconductor chip 20 from collet 10. However, since the air or nitrogen gas is easily charged with electrons, it is highly probable that a sudden stream of electric charges in the air or gas flows through chip pads 24 and fuses 26 to aligning stage 30. This electrostatic discharge current generates heat, passing through low resistive path of semiconductor chip 20, and the heat often causes the melting of gate polysilicon around the fuses 26, the breakdown of circuits or the destruction of chip pads 24. This problem becomes more serious when collet 10 is electrically nonconductive, and aligning stage 30 is electrically conductive.
FIG. 4 shows another example of ESD damage that arises when collet 10 is electrically conductive. As seen from FIG. 4, a combined operation of collet 10 and plunger 42 separates semiconductor chip 20 from sawing tape 40. While plunger 42 pushes up semiconductor chip 20, collet 10 picks up semiconductor chip 20. During this operation, electrostatic discharge forms in the wedge-shaped gap between sawing tape 40 and semiconductor chip 20, and flows to collet 10 via chip pads 24 and fuses 26 that are very close to contact part 18 of collet 10.
Damage to semiconductor chips from electrostatic discharge is likely to become a more serious problem in light of the continuing trend to higher circuit integration and narrower pattern width. One approach to solve the problem associated with electrostatic discharge is to cover the fuses with the passivation layer after repairing semiconductor wafers. However, this approach requires high level of cleanness in the electrical die sorting and consequently additional manufacturing costs. Besides, the chip pads should be exposed for wire-bonding.
Another approach modifies the architecture of the circuits so that each fuse is connected to an extra capacitor to prevent electrostatic discharge. However, this approach also increases the manufacturing cost.